In deep sub-micron semiconductor process technologies, interconnect delays can easily dominate gate propagation delays as major contributors to the total delay through signal paths of an integrated circuit device. Accordingly, it is important that interconnect delays, and in particular their associated resistance and capacitance ("R,C") parameters, be thoroughly and accurately accounted for in computer simulations of integrated circuit designs. Otherwise, unexpected timing problems in the resulting silicon may require time consuming and costly redesigns with little or no guidance on how to correct the problems.
One problem in accurately taking into account the effect of interconnect delays, however, is that interconnect material and geometry parameters are subject to significant process-induced variation. Although empirical data gathered from wafer samples fabricated in a given process provide distribution data for such process-induced variation, the determination of statistically worst case (i.e., "3-sigma" or "3-.sigma.") interconnect delays from such data is not straight-forward. Traditional skew-corner worst case analyses are computationally simple, but prove overly conservative.
One method different than such traditional skew-corner approach for obtaining statistically-based worst case delay and crosstalk for a critical net is described in "3-sigma Worst-Case Calculation of Delay and Crosstalk for Critical Net," by Norman Chang, Valery Kanevsky, Bill Queen, O. Sam Nakagawa, and Soo-Young Oh, presented at the 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems in Austin, Tex., on Dec. 4-5, 1997.
One problem with this method, however, is that it only provides worst case delay information for a critical net, and provides no useful information for other nets in the integrated circuit design. Another problem is that the obtained delay information is not applicable to other integrated circuit designs, or even the same integrated circuit design if a subsequent re-layout of the integrated circuit design results in the given net changing its length or route due to re-placement and/or re-routing of the integrated circuit design. Yet another problem is that this method is very slow since it employs extensive use of time consuming Monte Carlo circuit simulations via SPICE. Consequently, such method is generally inadequate for electronic design automation ("EDA") purposes.